The present invention relates in general to a sample and hold circuit, and more particularly to a wide-band sample and hold circuit for sampling and holding an analog input signal along two paths by a 1/2 frequency clock signal into which a sample and hold clock signal is frequency-divided by two and outputting the sampled and held signals under a switching control, so that the circuit can have sampling and holding intervals enough to meet a variation of the wide-band analog input signal and thus its operation can be performed at high speed.
A sample and hold circuit is conventionally used as an input stage of an analog/digital converter. Namely, for the purpose of conversion of an analog signal into a digital signal, the sample and hold circuit samples the analog signal during a half period of a sample and hold clock signal and holds a level of the final sampled signal during the half period.
With reference to FIG. 1, there is shown a block diagram of a conventional sample and hold circuit. The circuit comprises an input buffer 1 for inputting an analog input signal Vin, a switch SW1 for transferring or blocking an output signal from the input buffer 1 during a predetermined period in accordance with a sample and hold clock signal CLK of the predetermined period, a sample and hold condenser C for sampling an output signal from the switch SW1 and holding a level of the final sampled signal on the turning-off of the switch SW1, and an output buffer 2 for buffering an output signal from the sample and hold condenser C and outputting an output signal Vout.
The operation of the conventional sample and hold circuit with the above-mentioned construction will now be described with reference to FIGS. 2A through 2C.
First, if the analog input signal of waveform as shown in FIG. 2B is inputted to the input buffer 1 and the sample and hold clock signal CLK is applied to the control terminal of the switch SW1 as a pulse signal of the predetermined period as shown in FIG. 2A, the switch SW1 is turned on during the period that the sample and hold clock signal CLK is low, so that the analog input signal Vin inputted through the input buffer 1 is transferred to the sample and hold condenser C; the switch SW1 is turned off during the period that the sample and hold clock signal CLK is high, so that the output from the input buffer 1 being transferred to the sample and hold condenser is blocked. As a result, the sample and hold condenser C samples the analog input signal Vin being transferred through the input buffer 1 and the switch SW1 during the period that the switch SW1 is turned on. On the other hand, during the period that the switch SW1 is turned off, the sample and hold condenser C, because of the absence of a discharging loop, holds a level of the signal finally sampled during the just previous sampling period. As a result, the sample and hold condenser C samples and holds the analog input signal Vin as shown in FIG. 2B synchronously with the sample and hold clock signal CLK and outputs a sample and hold signal Vc as shown in FIG. 2C to the output buffer 2. Then, the sample and hold signal Vc is outputted as the output signal Vout by the output buffer 2.
However, if the level of the analog input signal Vin is reduced while the operation of the sample and hold condenser C is performed during the sampling period, there is present a discharging loop wherein the voltage charged on the sample and hold condenser C is discharged through the switch SW1. For this reason, in the high speed operation wherein the period of the sample and hold clock signal CLK is short, there occurs a case where the charging and discharging speeds of the sample and hold condenser C do not meet sufficiently the variation of the analog input signal Vin. If the capacity of the sample and hold condenser C is smaller in order to solve this problem, it is difficult for the sample and hold condenser C to hold a level of the sampled signal naturally due to a leakage current during the holding period wherein the level of the sampled signal must be held during a constant interval. As a result, the sample and hold condenser C can not help having a capacity enough not to be influenced by the leakage current during the holding period. This results in a restriction of the operation at high speed.